Diseño de PCB para fabricación (DFM): lista de fiabilidad

TL;DR: what DFM actually buys you

A prototype only has to work once, on your bench, while you watch it. A manufacturable, field-reliable industrial board has to survive a fab's etch and rout tolerances, a pick-and-place and reflow line it never sees you operate, and then years inside a hot, vibrating, electrically noisy cabinet. Design for Manufacturing (DFM) is the set of rules that closes the gap between those two worlds.

This is a checklist you can hand to a layout engineer or use to de-risk a quote before you commit to a fab and assembly run. Every rule below is framed the same way: the recommended value, the IPC standard it comes from, what fails if you ignore it, and where it bites — at the fab, at the assembly house, or six months into deployment.

DFM is not a code review you do once — it spans schematic, layout, and pre-fab

The single most expensive DFM mistake is treating it as a final gate. The cost of fixing a defect rises by roughly 10x at each stage it survives. A wrong footprint caught in the schematic costs a few minutes; the same error caught after a thousand-piece assembly run costs a respin, new stencils, and weeks of slipped schedule.

Run DFM at three points:

1. Schematic / part-selection — choose packages your assembler can place, define which nets get test points, fix connector pinouts and impedance-controlled nets. These are nearly free to change now.
2. Layout — enforce every geometric rule (clearance, annular ring, copper-to-edge, thermal relief, courtyard) with an automated Design Rule Check (DRC) before you route the last net.
3. Pre-fab — run a final DFM/DFA pass against your specific fab and assembler capability sheet, then export a clean package: Gerber X2 or ODB++, NC drill, IPC-356 netlist, assembly drawing, paste layers, and a costed BOM.

Skipping the schematic-stage and layout-stage reviews is why so many boards "pass" a hurried pre-fab check and still get bounced by the assembler's incoming DFM scan.

The DFM rule table: spec, standard, failure mode, and where it bites

This is the core of the checklist. Treat each row as a pass/fail gate, not a guideline. Values shown are sensible IPC Class 2 starting points for a standard 1.6 mm, 1 oz copper, 4-layer industrial IoT board; tighten them for Class 3 and confirm against your fab's capability sheet, because the fab's process limit always wins over a textbook number.

A page that gives a buyer this table plus a numbered procedure is exactly the kind of structured, checkable content engineers and procurement teams cite when they compare a layout against "what good looks like."

Annular ring and copper-to-edge: the two rules fabs reject on most

These are the geometric rules that cause outright fab rejection, not just yield loss.

Annular ring is the copper that remains around a drilled hole after the drill bit's real-world position error is subtracted. IPC-6012 Class 2 permits a small amount of tangency; Class 3 guarantees a minimum ring with no breakout. Drill registration on a multilayer board is not perfect — typical fabs hold drill-to-copper registration in the tens of microns — so if you design to a 0.05 mm ring with no margin, normal process variation eats it and you get breakout: the hole intersects the pad edge. On a via that carries current or sees thermal cycling (−40 to +85 °C industrial range), breakout is a latent open that shows up months later under vibration.

Copper-to-edge clearance is the gap between any copper and the board outline. The fab routs or V-scores the panel with a physical bit that has its own tolerance. Run copper to within 0.1 mm of the edge and the bit can expose it, raise a burr, or initiate delamination. The 0.25 mm (10 mil) minimum, widened to 0.5 mm for V-scored edges, keeps copper inside the rout tolerance band. This is the rule most likely to come back as a fab email asking you to revise the Gerbers before they'll run the job.

Thermal relief, silkscreen, and test points: the rules the assembly line enforces

These rules don't get rejected at fab — the board builds fine as bare copper — but they break at assembly.

• Thermal relief. A through-hole or large SMD pad tied directly to a copper plane acts as a heat sink. During reflow, the plane wicks heat away faster than the oven can deliver it, so the joint never reaches liquidus → cold joint, or one side of a 0402 lifts before the other wets → tombstoning. Spoke-style thermal relief (typically four spokes) on plane connections throttles that heat path so the joint reflows evenly. IPC-A-610 is the acceptance standard the line inspects against.
• Silkscreen over pads. Most fabs automatically clip silkscreen that overlaps a solderable pad, because ink on a pad ruins the joint. The side effect is that your reference designators vanish, and now the assembler — and every future repair tech — can't identify components. Keep silk ≥0.15 mm off every pad.
• Test points. Without a test point on each net, you can't run in-circuit or flying-probe test, and you have nowhere to land a probe during bring-up. Defects then ship as field escapes. Give every net a test point of at least 0.9 mm (35 mil) diameter, keep them on one side where you can, and you make the board testable and debuggable for its whole life.

Panelization and fiducials: an un-panelized board is an un-buildable board

Pick-and-place machines do not handle loose, oddly shaped boards. They handle panels with straight rails and registration marks. If you hand an assembler a single un-panelized board with no fiducials, the line either stops or hand-builds it at a premium.

Provide:

• Rails: ~5 mm break-off or V-scored rails on at least two opposite edges to give the conveyor and clamps something to grip.
• Global fiducials: at least three, non-collinear, near the panel corners — a 1 mm copper dot inside a 2 mm soldermask opening — so the machine can correct for panel skew and scaling.
• Local fiducials: on fine-pitch (≤0.5 mm) and BGA parts, so placement accuracy is referenced to the part, not just the panel.
• Tooling holes and adequate copper-to-edge so the depanel step doesn't stress joints.

Panelization is also where assembly cost is won or lost: an efficient array of boards on a standard panel size amortizes stencil, setup, and handling across more units per pass.

Controlled impedance: the rule that fails in the field, not at the bench

For an industrial IoT board, the highest-frequency content is usually the 2.4 GHz Wi-Fi/BLE radio (e.g. an ESP32 or ESP32-S3 module), USB, and any wired Ethernet. These are the nets where geometry stops being a wiring problem and becomes a transmission-line problem.

• The RF feed from an ESP32/ESP32-S3 to its antenna or U.FL connector should be a 50 Ω single-ended trace (typically coplanar waveguide with ground) with a continuous reference plane and a keep-out under the PCB antenna. Detune it and you lose range and may fail radiated emissions.
• USB 2.0 D+/D− is a 90 Ω differential pair; length-match it and keep it over solid ground.
• Ethernet pairs are 100 Ω differential.

Impedance is set by trace width, dielectric height, and the dielectric constant (Dk) of the stack-up — which is why controlled impedance is a stack-up and fab conversation, not just a routing one. You specify the target impedance, the fab adjusts trace width to hit it on their measured material, and they coupon-test it. Skip this and the board passes every bench test, then fails FCC/CE radiated emissions or shows intermittent USB retrains in the field — the most expensive place to discover it.

Reuse the rule, declare the class, and confirm the fab's capability

Two habits separate teams that respin once from teams that respin three times:

1. Declare your IPC class on the fab and assembly drawing (e.g. "IPC-6012 Class 2, IPC-A-610 Class 2"). The class tells the fab and assembler which acceptance limits to inspect against. Designing to Class 3 geometry but ordering Class 2 inspection means you paid for margin nobody verifies.
2. Always reconcile your DRC against the chosen vendor's capability sheet. A 2 mil annular ring or 4 mil trace is meaningless if your fab's economical process is 5 mil. The vendor's real process limit is the rule; the IPC table is the floor.

Do both, run the three-stage review, and the board that comes off the line behaves like the one on your bench — at production volume, across temperature, for years.

FAQ

What IPC class should an industrial IoT PCB target, and what does it actually change?

Most industrial IoT boards should be fabricated and assembled to IPC Class 2 (IPC-6012 for the bare board, IPC-A-610 Class 2 for assembly), which is the default "dedicated service electronics" tier and what almost every contract manufacturer quotes by default. Class 2 allows reduced-but-defined acceptance limits — for example, it tolerates a smaller minimum annular ring and some solder-joint cosmetic variation that Class 3 rejects. Move to IPC Class 3 only when the board goes into safety-critical, high-vibration, or continuous-uptime service (wide thermal cycling, −40 to +85 °C, or equipment where a field failure is dangerous or very expensive). Class 3 tightens annular ring, plating thickness, via fill, and solder-joint criteria, and it typically adds 15–40% to fab and assembly cost. The class you pick changes acceptance limits and inspection rigor, not the laws of physics — so you still have to design to the rule, then declare the class so the fab and assembler inspect to the same bar you designed to.

What are the most common DFM mistakes that get a board rejected at the assembly house?

The recurring offenders are: (1) no test points or fiducials, so the assembler cannot machine-place or test the board; (2) silkscreen printed over pads, which the fab clips automatically and which leaves you with unreadable reference designators; (3) insufficient copper-to-edge clearance, which exposes copper at the panel rout and risks shorts and delamination; (4) thermal pads with no thermal relief, which the reflow oven cannot bring up to temperature, producing cold or tombstoned joints; and (5) parts placed too close together or too near the board edge to clear the pick-and-place nozzle and the panel rails. Most of these are caught by a proper DFM review before Gerber release, which is exactly why assembly houses run an automated DFM check on every incoming job and will pause the line — and your schedule — if it fails.

How early should DFM review happen — at schematic, layout, or pre-fab?

DFM is not a single pre-fab gate; it spans all three stages, and the cost of a miss rises by roughly an order of magnitude at each stage. At schematic you lock the decisions that are nearly free to change now and very expensive later: package/footprint selection, test-point nets, connector pinouts, and impedance-controlled net definitions. At layout you enforce the geometric rules — clearances, annular ring, copper-to-edge, thermal relief, courtyards — using the design-rule check (DRC). Pre-fab you run a final DFM/DFA pass against the specific fab and assembler capabilities and generate a clean fabrication package (Gerber X2 or ODB++, drill, IPC netlist, assembly drawing, BOM, paste layers). Catching a footprint error in the schematic costs minutes; catching it after a 1,000-piece assembly run costs a respin and weeks of slipped schedule.

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De-risking a custom board before you commit to a fab run? GizanTech designs custom PCBs and ESP32/ESP32-S3 firmware for industrial IoT, automation, and agri-tech, and we run this DFM and reliability checklist at the schematic, layout, and pre-fab stages — so the board that comes off the line is the one that survives the field. See our PCB design service or talk to our engineering team.